53 lines
922 B
Coq
53 lines
922 B
Coq
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/*
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* This tests is based on PR#434
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*/
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`define VAR1 2
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`define VAR2 5
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module mctrl( reset0, reset1, reset2, reset3, clk, por);
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output reset0, reset1, reset2, reset3;
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input clk,por;
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reg [7:0] cnt;
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always @ (posedge por or posedge clk)
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if (por)
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cnt <= 0;
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else
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cnt <= cnt+1;
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assign reset0 = (cnt == `VAR1);
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assign reset1 = (cnt == `VAR2);
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assign reset2 = (cnt == `VAR1 + `VAR2);
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assign reset3 = (cnt == `VAR1 + `VAR2 + 2);
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endmodule
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`timescale 1ns/1ps
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module test();
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reg clk,por;
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wire reset0, reset1, reset2, reset3;
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mctrl m1(reset0, reset1, reset2, reset3, clk, por);
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initial
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begin
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clk = 0;
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por = 0;
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$monitor($time,, "reset0=%b, reset1=%b, reset2=%b, reset3=%b",
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reset0, reset1, reset2, reset3);
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#1000 $finish(0);
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end
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always #15 clk = ~clk;
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initial
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begin
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#10 por = 1;
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#10 por = 0;
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end
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endmodule // test
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