78 lines
2.0 KiB
Coq
78 lines
2.0 KiB
Coq
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/*
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* Copyright (c) 2001 Ted Bullen
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// This code is released to Steve Williams for the Icarus Verilog compiler
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// It can be used as desired !
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// DEFINES
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`define NRBITS 4 // Number of bits in each operand
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// TOP MODULE
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module testFunction();
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// SIGNAL DECLARATIONS
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reg clock;
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reg [`NRBITS-1:0] a_in;
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integer a_integer;
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integer myint;
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reg [`NRBITS:0] cycle_count; // Counts valid clock cycles
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// Initialize inputs
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initial begin
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clock = 1;
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cycle_count = 0;
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# (16*200+15) $display("PASSED");
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$finish;
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end
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// Generate the clock
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always #100 clock = ~clock;
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// Simulate
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always @(negedge clock) begin
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cycle_count = cycle_count + 1;
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// Create inputs between 0 and all 1s
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a_in = cycle_count[`NRBITS-1:0];
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myint = a_in;
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$display("a_in = %d, myint = %d", a_in, myint);
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// Convert the unsigned numbers to signed numbers
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a_integer = short_to_int(a_in);
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if (myint !== a_integer)
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begin
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$display("ERROR ! %d !== %d", myint, a_integer);
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$stop;
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end
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end
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// Function to convert a reg of `NRBITS
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// bits to a signed integer
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function integer short_to_int;
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input [`NRBITS-1:0] x;
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begin
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short_to_int = x;
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$display("\tshort_to_int(%b) = %b", x, short_to_int);
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end
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endfunction
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endmodule
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