47 lines
894 B
Coq
47 lines
894 B
Coq
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`timescale 1ns/10ps
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module top;
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reg pass, clk;
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wire out;
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initial begin
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$monitor("%f %b %b", $realtime, out, clk);
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pass = 1'b1;
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$sdf_annotate("ivltests/pr2972866.sdf", dut);
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clk = 1'b0;
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#10 clk = 1'b1;
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#10 clk = 1'b0;
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// Don't check for just PASSED since we are looking for modpath
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// problems (SDF WARNING)!
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#10 if (pass) $display("Simulation ran correctly.");
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end
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always @(out) if (out !== clk && $time != 0) begin
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$display("Failed to match, expected %b, got %b.", clk, out);
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pass = 1'b0;
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end
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ckt dut (out, clk);
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endmodule
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module ckt(clk_out, clk_in);
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output clk_out;
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input clk_in;
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wire clk_l1;
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CLK_BUF L1 (clk_l1, clk_in);
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CLK_BUF L2 (clk_out, clk_l1);
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endmodule
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module CLK_BUF(out, in);
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output out;
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input in;
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buf b1 (out, in);
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specify
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(in +=> out) = (0.1:0.1:0.1, 0.1:0.1:0.1);
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endspecify
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endmodule
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