49 lines
1.1 KiB
Coq
49 lines
1.1 KiB
Coq
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// This program is based on pr2138979. In particular, the signed
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// expressions are sign-extended before the '|' is evaluated. This
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// behavior is verified by modelsim and ncverilog. (It appears that
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// gplcver gets this wrong.)
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module main;
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reg [7:0] a, b;
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wire [15:0] y;
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reg [15:0] z;
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// Use $signed() to sign extend operands before logic OR
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// - Note that Icarus Verilog is not sign extending as expected
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assign y = $signed(a) | $signed(b);
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initial begin
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a = 8'h55;
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b = 8'haa;
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z = $signed(a) | $signed(b);
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#1 if (y !== 16'hff_ff || y !== z) begin
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$display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
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$finish;
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end
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a = 8'haa;
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b = 8'h55;
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z = $signed(a) | $signed(b);
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#1 if (y !== 16'hff_ff || y !== z) begin
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$display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
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$finish;
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end
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a = 8'h7f;
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b = 8'h00;
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z = $signed(a) | $signed(b);
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#1 if (y !== 16'h00_7f || y !== z) begin
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$display("FAILED -- a=%h, b=%h, y=%h, z=%h", a, b, y, z);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule
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