20 lines
234 B
Coq
20 lines
234 B
Coq
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module top;
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reg clk = 0;
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reg [1:0] in = 2'b00;
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wire [1:0] out;
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test t1 (clk, out, in);
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endmodule
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module test(clk, a, b);
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input clk;
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output a;
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input [1:0] b;
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reg [1:0] a;
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always @(posedge clk) begin
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a <= b;
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end
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endmodule
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