84 lines
1.4 KiB
Coq
84 lines
1.4 KiB
Coq
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// This is a compile time test,
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// for various port declaration syntax options
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`define TEST3
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// `define TEST3_X
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// unconnected ports
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`ifdef TEST3
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module port_3
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(
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dummy_1,
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/* unconnected */,
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in[7:0],
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dummy_2,
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out[7:0],
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/* unconnected */
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);
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input [7:0] in;
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output [7:0] out;
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output dummy_1;
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output dummy_2;
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assign out = in;
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endmodule
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`endif // ifdef TEST_3
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module port_test;
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reg [7:0] data;
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`ifdef TEST3
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wire [7:0] out_3;
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reg pass_3;
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initial pass_3 = 1;
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port_3 dut_3
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(, // unconnected dummy_1
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`ifdef TEST3_X
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// This fails in verilog-XL with:
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// Error! Expression given for a null module port [Verilog-EXPNMP]
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// "port-test.v", 115: dut_3(, pass_3, data[7:0], ,
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// out_3[7:0], )
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pass_3, // dummy unconnected
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`else
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, // unconnected unconnected
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`endif
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data[7:0],
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, // unconnected dummy_2
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out_3[7:0],
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// unconnected unconnected
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);
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`endif
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initial
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begin
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data <= 1;
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#1;
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while (data != 0)
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begin
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$display ("%b", data);
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`ifdef TEST3
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if (out_3 != data)
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begin
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$display("data=%b, out_2=%b, FAILED", data, out_3);
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pass_3 = 0;
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end
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`endif
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data <= data << 1;
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#1;
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end
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`ifdef TEST3
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if (pass_3)
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$display("PASSED");
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`endif
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$finish;
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end
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endmodule // port_test
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