18 lines
386 B
Coq
18 lines
386 B
Coq
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// Tests that it possible to omit the initial `parameter` keyword in a parameter
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// port list in SystemVerilog. In Verilog this is not allowed and should result
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// in an error.
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module a #(integer A = 1);
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initial begin
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if (A == 10) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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module test;
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a #(.A(10.1)) i_a();
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endmodule
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