32 lines
547 B
Coq
32 lines
547 B
Coq
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module main;
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reg [7:0] mem;
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reg [2:0] addr;
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reg out;
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reg clk;
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(* ivl_synthesis_on *)
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always @(posedge clk) out <= mem[addr];
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integer idx;
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(* ivl_synthesis_off *)
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initial begin
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mem = 8'hca;
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addr = 0;
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clk = 0;
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for (idx = 0 ; idx < 8 ; idx = idx+1) begin
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addr = idx[2:0];
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#1 clk = 1;
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#1 clk = 0;
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if (out !== mem[idx]) begin
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$display("FAILED -- mem[%d] = %b", idx, out);
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$finish;
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end
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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