78 lines
1.5 KiB
Coq
78 lines
1.5 KiB
Coq
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module main;
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reg [7:0] a;
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reg [2:0] adr, w_adr;
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reg rst, clk, ae, wr;
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(* ivl_synthesis_on *)
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always @(posedge clk)
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if (rst) begin
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a <= 8'b00000000;
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adr <= 3'b000;
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end else if (ae) begin
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adr <= w_adr;
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end else if (wr) begin
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adr <= adr + 1;
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a[adr] <= 1;
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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wr = 0;
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ae = 0;
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rst = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (a !== 8'b0000_0000 || adr !== 3'b000) begin
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$display("FAILED - reset - a=%b, adr=%b", a, adr);
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$finish;
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end
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rst = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (a !== 8'b0000_0000 || adr !== 3'b000) begin
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$display("FAILED - pause - a=%b, adr=%b", a, adr);
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$finish;
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end
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wr = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (a !== 8'b0000_0001 || adr !== 3'b001) begin
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$display("FAILED - wr 1 - a=%b, adr=%b", a, adr);
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$finish;
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end
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#1 clk = 1;
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#1 clk = 0;
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if (a !== 8'b0000_0011 || adr !== 3'b010) begin
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$display("FAILED - wr 2 - a=%b, adr=%b", a, adr);
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$finish;
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end
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ae = 1;
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w_adr = 4;
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#1 clk = 1;
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#1 clk = 0;
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if (a !== 8'b0000_0011 || adr !== 3'b100) begin
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$display("FAILED - ae - a=%b, adr=%b", a, adr);
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$finish;
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end
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ae = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (a !== 8'b0001_0011 || adr !== 3'b101) begin
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$display("FAILED - ae - a=%b, adr=%b", a, adr);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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