42 lines
644 B
Coq
42 lines
644 B
Coq
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module main;
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reg clk;
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reg mem[1:0];
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reg clr;
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(* ivl_synthesis_on *)
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always @(posedge clk)
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if (clr) begin
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mem[1] <= 1;
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mem[0] <= 0;
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end else begin
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mem[1] <= ~mem[1];
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mem[0] <= ~mem[0];
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end
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(* ivl_synthesis_off *)
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initial begin
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clk = 0;
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clr = 1;
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#1 clk = 1;
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#1 clk = 0;
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if (mem[0] !== 0 || mem[1] !== 1) begin
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$display("FAILED -- clr");
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$finish;
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end
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clr = 0;
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#1 clk = 1;
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#1 clk = 0;
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if (mem[0] !== 1 || mem[1] !== 0) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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