59 lines
1.8 KiB
Coq
59 lines
1.8 KiB
Coq
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module main;
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reg clk, rst, done;
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wire [31:0] x;
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reg [3:0] a;
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reg [23:0] in, out;
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reg [2:0] a_fifo_cam_indices[3:0], lt_fifo_cam_indices[3:0];
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// Debug signals to see 'em under signalscan
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// -- iverilog generates a warning here
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wire [2:0] db0_a_fifo_cam_indices = a_fifo_cam_indices[0];
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// generate a clock
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always
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#10 clk = ~clk;
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// -- iverilog generates a warning here
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assign x[31:0] = { 28'hfffffff, (~a[3:0] + 4'd1) };
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initial
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begin
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$display ("\n<< BEGIN >>");
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rst = 1'b0;
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a[3:0] = 4'b0101;
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// -- iverilog internal value is not dealt with correctly (see value
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out[23:0] = ( rst ? 24'o7654_3210 : in[23:0] );
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casex ( done )
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// -- iverilog generate errors - "could not match signal"
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1'b1: { a_fifo_cam_indices[3],
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a_fifo_cam_indices[2],
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a_fifo_cam_indices[1],
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a_fifo_cam_indices[0] } = {3'b000,
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lt_fifo_cam_indices[3],
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lt_fifo_cam_indices[2],
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lt_fifo_cam_indices[1]};
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1'b0: { a_fifo_cam_indices[3],
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a_fifo_cam_indices[2],
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a_fifo_cam_indices[1],
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a_fifo_cam_indices[0] } = { lt_fifo_cam_indices[3],
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lt_fifo_cam_indices[2],
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lt_fifo_cam_indices[1],
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lt_fifo_cam_indices[0]};
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endcase
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$display ("\n<< END >>");
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$finish(0);
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end
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// Waves definition
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// initial
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// begin
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// $dumpfile("out.dump");
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// $dumpvars(0, main);
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// end
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endmodule // main
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