44 lines
909 B
VHDL
44 lines
909 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity gxor is
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port (a, b: in std_logic;
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z : out std_logic);
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end gxor;
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architecture gxor_rtl of gxor is
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begin
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z <= a xor b;
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end architecture gxor_rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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entity gxor_reduce is
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generic (half_width: integer := 4);
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port (a: in std_logic_vector (2*half_width-1 downto 0);
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ar: out std_logic);
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end gxor_reduce;
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architecture gxor_reduce_rtl of gxor_reduce is
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component gxor is
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port (a, b: in std_logic;
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z : out std_logic);
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end component;
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--type path is array (0 to size/2) of std_logic;
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signal x_int: std_logic_vector (2*half_width downto 0);
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begin
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x_int(2*half_width) <= '0'; -- MSB
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gen_xor: for i in 2*half_width downto 1 generate
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each_gate: gxor port map (a => x_int(i), b => a(i-1), z => x_int(i-1) );
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end generate;
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ar <= x_int(0);
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end architecture gxor_reduce_rtl;
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