59 lines
1.5 KiB
Coq
59 lines
1.5 KiB
Coq
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/*
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Steve,
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I have small 8bit CPU working in Iverilog, it works if I
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change a line similar to the one below in the test case to
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assign result = (data[0] | data[1]) ? 1:0;
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using the test case below I get,
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elab_net.cc:1368: failed assertion `expr_sig->pin_count() == 1'
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when compiling using the standard "verilog bug.v" (verilog-20000519)
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This works fine in XL.
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Regards
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Gerard.
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PS thanks for fixing the $monitor function. It works as XL,
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as long as I pipe the output through uniq (./stimexe | uniq)
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*/
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module stim;
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wire [1:0] data;
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wire result;
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assign result = data ? 1:0;
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initial
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$display("PASSED");
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endmodule // stim
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/*
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* Copyright (c) 2000 Gerard A. Allan (gaa@ee.ed.ac.uk)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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