41 lines
746 B
Coq
41 lines
746 B
Coq
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/*
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*/
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module main;
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reg [1:0] sel, in;
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reg [1:0] out;
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(* ivl_combinational *)
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always @*
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(* ivl_full_case *) case (sel)
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2'b01: out = 2'b10;
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2'b10: out = in[0];
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2'b11: out = in[1];
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endcase // casex(sel)
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(* ivl_synthesis_off *)
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initial begin
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in = 2'b10;
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sel = 1;
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#1 if (out !== 2'b10) begin
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$display("FAILED -- sel=%b, out=%b", sel, out);
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$finish;
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end
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sel = 2;
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#1 if (out !== 2'b00) begin
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$display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
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$finish;
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end
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sel = 3;
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#1 if (out !== 2'b01) begin
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$display("FAILED -- sel=%b, in=%b, out=%b", sel, in, out);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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