27 lines
625 B
VHDL
27 lines
625 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity dec2to4 is
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port (sel: in std_logic_vector (1 downto 0);
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en: in std_logic;
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y: out std_logic_vector (0 to 3) );
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end dec2to4;
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architecture dec2to4_rtl of dec2to4 is
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begin
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process (sel, en)
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begin
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if (en = '1') then
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case sel is
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when "00" => y <= "1000";
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when "01" => y <= "0100";
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when "10" => y <= "0010";
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when "11" => y <= "0001";
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when others => y <= "0000";
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end case;
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else
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y <= "0000";
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end if;
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end process;
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end dec2to4_rtl;
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