34 lines
1.1 KiB
Coq
34 lines
1.1 KiB
Coq
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/*
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* This is a reduced example from comp1001 to demonstrate a problem
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* in the Icarus Verilog code generator. If the left && argument is
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* replaced with a single 1'b1 which should be logically equivalent
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* this will work correctly. It appears that the width of the
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* expression is being calculated incorrectly.
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*/
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module top;
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reg [119:110] r163;
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reg [192:162] r222;
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initial begin
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r163 = 10'h17d;
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r222 = (1'b1 + (22'h3a15 && ((^r163) < 4'h8))) != 1'bx;
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// ... the subexpression ^r163 is the 1-bit value 1'b1
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// = (1'b1 + (22'h3a15 && ((1'b1) < 4'h8))) != 1'bx
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// ... the operands of && are self determined, but the widths of the
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// operands of < must match
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// = (1'b1 + (22'h3a15 && (4'h1 < 4'h8))) != 1'bx
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// ... The && is a 1'bit result.
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// = (1'b1 + 1'b1) != 1'bx
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// ... Operands of != are sized to max of i and j, namely 1 in this case.
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// = 1'b0 != 1'bx
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// = 1'bx
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// ... but the result is 31 bits, so the result is...
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// = 31'b0x
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if (r222 !== 31'b0x) $display("FAILED -- r222=%b", r222);
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else $display("PASSED");
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end
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endmodule
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