81 lines
2.6 KiB
Coq
81 lines
2.6 KiB
Coq
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module test
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(output reg [4:0] q,
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input wire [31:0] sel
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/* */);
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always @* begin
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casez (sel)
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32'b1zzz_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd0;
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32'b01zz_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd1;
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32'b001z_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd2;
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32'b0001_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd3;
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32'b0000_1zzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd4;
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32'b0000_01zz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd5;
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32'b0000_001z_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd6;
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32'b0000_0001_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd7;
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32'b0000_0000_1zzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd8;
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32'b0000_0000_01zz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd9;
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32'b0000_0000_001z_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd10;
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32'b0000_0000_0001_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd11;
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32'b0000_0000_0000_1zzz__zzzz_zzzz_zzzz_zzzz: q = 5'd12;
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32'b0000_0000_0000_01zz__zzzz_zzzz_zzzz_zzzz: q = 5'd13;
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32'b0000_0000_0000_001z__zzzz_zzzz_zzzz_zzzz: q = 5'd14;
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32'b0000_0000_0000_0001__zzzz_zzzz_zzzz_zzzz: q = 5'd15;
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32'b0000_0000_0000_0000__1zzz_zzzz_zzzz_zzzz: q = 5'd16;
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32'b0000_0000_0000_0000__01zz_zzzz_zzzz_zzzz: q = 5'd17;
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32'b0000_0000_0000_0000__001z_zzzz_zzzz_zzzz: q = 5'd18;
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32'b0000_0000_0000_0000__0001_zzzz_zzzz_zzzz: q = 5'd19;
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32'b0000_0000_0000_0000__0000_1zzz_zzzz_zzzz: q = 5'd20;
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32'b0000_0000_0000_0000__0000_01zz_zzzz_zzzz: q = 5'd21;
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32'b0000_0000_0000_0000__0000_001z_zzzz_zzzz: q = 5'd22;
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32'b0000_0000_0000_0000__0000_0001_zzzz_zzzz: q = 5'd23;
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32'b0000_0000_0000_0000__0000_0000_1zzz_zzzz: q = 5'd24;
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32'b0000_0000_0000_0000__0000_0000_01zz_zzzz: q = 5'd25;
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32'b0000_0000_0000_0000__0000_0000_001z_zzzz: q = 5'd26;
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32'b0000_0000_0000_0000__0000_0000_0001_zzzz: q = 5'd27;
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32'b0000_0000_0000_0000__0000_0000_0000_1zzz: q = 5'd28;
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32'b0000_0000_0000_0000__0000_0000_0000_01zz: q = 5'd29;
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32'b0000_0000_0000_0000__0000_0000_0000_001z: q = 5'd30;
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32'b0000_0000_0000_0000__0000_0000_0000_0001: q = 5'd31;
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default: q = 5'd0;
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endcase
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end // always @ *
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endmodule // test
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module main;
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reg [31:0] sel;
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wire [4:0] q;
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test dut (.q(q), .sel(sel));
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integer idx;
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integer rept;
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reg [31:0] mask, setb;
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initial begin
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sel = 0;
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#1 if (q !== 5'd0) begin
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$display("FAILED -- sel=%b, q=%b", sel, q);
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$finish;
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end
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for (idx = 0 ; idx < 32 ; idx = idx+1) begin
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mask = 32'h7fff_ffff >> idx;
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setb = mask + 32'd1;
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for (rept = 0 ; rept < 4 ; rept = rept+1) begin
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sel = setb | (mask & $random);
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#1 if (q !== idx[4:0]) begin
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$display("FAILED -- sel=%b, q=%b, idx=%0d", sel, q, idx);
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$finish;
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end
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end
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end
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$display("PASSED");
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end
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endmodule
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