18 lines
277 B
Coq
18 lines
277 B
Coq
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`timescale 1ns/1ns
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module top;
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reg itrig = 1'b0;
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wire [31:0] tm, stm;
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assign tm = itrig * $time;
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assign stm = itrig * $stime;
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initial begin
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$monitor(tm,, stm);
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#1 itrig = 1'b1;
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#1 itrig = 1'b0;
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#1 itrig = 1'b1;
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#1 itrig = 1'b0;
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end
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endmodule
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