20 lines
401 B
VHDL
20 lines
401 B
VHDL
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-- Reduced test case, bug originally found in 4DSP's fmc110_ctrl.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity bug3 is
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port (
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sel : in std_logic_vector(3 downto 0);
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value : in std_logic;
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spi_sdo : out std_logic
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);
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end bug3;
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architecture bug3_syn of bug3 is
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begin
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-- no problem if the "not" is taken out
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spi_sdo <= not or_reduce(sel);
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end bug3_syn;
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