60 lines
1.6 KiB
Coq
60 lines
1.6 KiB
Coq
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module test;
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reg fail = 1'b0;
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reg [3:0] bus = 4'b0;
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initial begin
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// Check the initial value.
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if (bus !== 4'b0) begin
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$display("FAILED: initial value, got %b, expected 0000.", bus);
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fail = 1'b1;
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end
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// Check a bit assign and verify a normal bit assign does nothing.
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#1 assign bus[0] = 1'b1;
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bus[0] = 1'bz;
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if (bus !== 4'b0001) begin
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$display("FAILED: assign of bus[0], got %b, expected 0001.", bus);
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fail = 1'b1;
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end
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// Check a part assign.
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#1 assign bus[3:2] = 2'b11;
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if (bus !== 4'b1101) begin
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$display("FAILED: assign of bus[3:2], got %b, expected 1101.", bus);
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fail = 1'b1;
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end
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// Check that we can change an unassigned bit.
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#1 bus[1] = 1'bz;
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if (bus !== 4'b11z1) begin
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$display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus);
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fail = 1'b1;
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end
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// Check a bit deassign.
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#1 deassign bus[0];
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bus = 4'b000z;
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if (bus !== 4'b110z) begin
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$display("FAILED: deassign of bus[0], got %b, expected 110z.", bus);
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fail = 1'b1;
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end
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// Check a part deassign (we keep the old value if not changed).
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#1 deassign bus[3:2];
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bus[3] = 1'b0;
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if (bus !== 4'b010z) begin
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$display("FAILED: deassign of bus[3:2], got %b, expected 010z.", bus);
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fail = 1'b1;
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end
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// Check an assign from the upper thread bits >= 8.
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#1 assign bus[2:1] = 2'bx1;
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if (bus !== 4'b0x1z) begin
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$display("FAILED: assign of bus[2:1], got %b, expected 0x1z.", bus);
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fail = 1'b1;
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end
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if (!fail) $display("PASSED");
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end
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endmodule
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