iverilog/ivtest/gold/gate_connect2.gold

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./ivltests/gate_connect2.v:10: error: Expression width 32 does not match width 1 of logic gate array port 2.
./ivltests/gate_connect2.v:11: error: Expression width 2 does not match width 1 of logic gate array port 2.
./ivltests/gate_connect2.v:12: error: Expression width 2 does not match width 1 of logic gate array port 2.
3 error(s) during elaboration.