16 lines
204 B
Coq
16 lines
204 B
Coq
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`timescale 100 ps / 10 ps
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(* ivl_synthesis_cell *)
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module LD (Q, D, G);
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output Q;
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reg q_out;
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input D, G;
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buf b1 (Q, q_out);
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always @(D or G) if (G) q_out <= D;
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endmodule
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