42 lines
972 B
Coq
42 lines
972 B
Coq
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/*
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* This is a post-synthesis test for the blif_sign_ext.v test. Run this
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* simulation in these steps:
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*
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* $ iverilog -tblif -o foo.blif blif_sign_ext.v
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* $ abc
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* abc 01> read_blif foo.blif
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* abc 02> write_verilog foo.v
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* abc 03> quit
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* $ iverilog -g2009 -o foo.vvp blif_sign_ext_tb.v foo.v
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* $ vvp foo.vvp
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*/
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module main;
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parameter W=3, WO=5;
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reg signed [W:0] D;
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reg signed [WO:0] q;
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wire [WO:0] Q;
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sign_ext se(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]),
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.\Q[5] (Q[5]), .\Q[4] (Q[4]), .\Q[3] (Q[3]), .\Q[2] (Q[2]), .\Q[1] (Q[1]), .\Q[0] (Q[0]));
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int ddx;
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initial begin
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for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1) begin
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D = ddx[W:0];
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q = D;
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$display("D = %b, q = %b", D, q);
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#1;
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if (Q !== q) begin
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$display("FAILED -- D=%b, Q=%b (should be %b)", D, Q, q);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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