45 lines
1.1 KiB
Coq
45 lines
1.1 KiB
Coq
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module main;
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localparam WID = 4;
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reg [WID:0] X;
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wire q_and, q_or, q_xor, q_nand, q_nor, q_xnor;
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test_logic DUT(.\A[3] (X[3]), .\A[2] (X[2]), .\A[1] (X[1]), .\A[0] (X[0]),
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.q_and(q_and), .q_or(q_or), .q_xor(q_xor),
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.q_nand(q_nand), .q_nor(q_nor), .q_xnor(q_xnor));
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initial begin
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for (X = 0 ; X < 16 ; X = X+1) begin
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#1 /* Let gates settle. */;
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if (q_and !== & X[WID-1:0]) begin
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$display("FAILED -- q_and=%b, X=%b", q_and, X[WID-1:0]);
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$finish;
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end
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if (q_or !== | X[WID-1:0]) begin
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$display("FAILED -- q_or=%b, X=%b", q_or, X[WID-1:0]);
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$finish;
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end
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if (q_xor !== ^ X[WID-1:0]) begin
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$display("FAILED -- q_xor=%b, X=%b", q_xor, X[WID-1:0]);
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$finish;
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end
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if (q_nand !== ~& X[WID-1:0]) begin
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$display("FAILED -- q_nand=%b, X=%b", q_nand, X[WID-1:0]);
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$finish;
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end
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if (q_nor !== ~| X[WID-1:0]) begin
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$display("FAILED -- q_nor=%b, X=%b", q_nor, X[WID-1:0]);
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$finish;
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end
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if (q_xnor !== ~^ X[WID-1:0]) begin
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$display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[WID-1:0]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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