26 lines
629 B
VHDL
26 lines
629 B
VHDL
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--
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-- Author: Pawel Szostek (pawel.szostek@cern.ch)
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-- Date: 28.07.2011
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dummy is
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port (
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input : in std_logic_vector(7 downto 0);
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output : out std_logic_vector(7 downto 0)
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);
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end;
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architecture behaviour of dummy is
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begin
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L: process(input)
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variable tmp : std_logic_vector(7 downto 0);
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begin
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tmp := input; -- use multiple assignments to the same variable
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tmp := (7 => input(7), others => '1'); -- inluding slices in a process
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output <= tmp;
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end process;
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end;
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