52 lines
1.3 KiB
Coq
52 lines
1.3 KiB
Coq
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module test;
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// Check that the right hand side for a shift instruction is always treated as
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// unsigned. Even if its a signed register, or a transformation thereof.
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reg failed = 1'b0;
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`define check(val, exp) \
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if ((val) !== (exp)) begin \
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$display("FAILED(%0d): `%s`, expected `%0d`, got `%0d`.", `__LINE__, \
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`"val`", (exp), (val), 4); \
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failed = 1'b1; \
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end
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reg signed [1:0] shift = 2'b10;
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initial begin
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`check(1 << shift, 4)
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`check(1 << shift[1:0], 4)
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`check(2 << shift[1], 4)
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`check(1 << $unsigned(shift), 4)
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`check(1 << $signed(shift), 4)
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`check(1 << {shift}, 4)
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`check(1 <<< shift, 4)
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`check(1 <<< shift[1:0], 4)
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`check(2 <<< shift[1], 4)
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`check(1 <<< $unsigned(shift), 4)
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`check(1 <<< $signed(shift), 4)
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`check(1 <<< {shift}, 4)
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`check(16 >> shift, 4)
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`check(16 >> shift[1:0], 4)
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`check(8 >> shift[1], 4)
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`check(16 >> $unsigned(shift), 4)
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`check(16 >> $signed(shift), 4)
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`check(16 >> {shift}, 4)
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`check(16 >>> shift, 4)
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`check(16 >>> shift[1:0], 4)
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`check(8 >>> shift[1], 4)
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`check(16 >>> $unsigned(shift), 4)
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`check(16 >>> $signed(shift), 4)
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`check(16 >>> {shift}, 4)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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