82 lines
2.3 KiB
Coq
82 lines
2.3 KiB
Coq
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///////////////////////////////////////////////////////////////////////////
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//
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// To test:
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// (a) The use & representation of time variables
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// (b) The display of time variables
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//
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// Compile and run the program
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// iverilog tt_clean.v
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// vvp a.out
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//
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// VISUALLY INSPECT the displays. (There ain't no way to automate this)
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//
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///////////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 10 ps
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`define PCI_CLK_PERIOD 15.0 // 66 Mhz
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module top;
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reg PCI_Clk;
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reg fail;
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initial PCI_Clk <= 0;
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always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk;
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initial begin
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fail = 0;
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$display("\n\t\t==> CHECK THIS DISPLAY ==>\n");
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$display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
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$display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
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if($time !== 0) fail = 1;
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if (fail == 1)
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$display("$time=%0d (0)", $time);
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delay_pci(3);
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if($simtime !== 4500) fail = 1;
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if($time !== 45) fail = 1;
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if (fail == 1)
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$display("$time=%0d (45)", $time);
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#15;
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if($simtime !== 6000) fail = 1;
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if($time !== 60) fail = 1;
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#(`PCI_CLK_PERIOD);
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if($simtime !== 7500) fail = 1;
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if($time !== 75) fail = 1;
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#(`PCI_CLK_PERIOD *2);
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if($simtime !== 10500) fail = 1;
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if($time !== 105) fail = 1;
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$timeformat(-9,2,"ns",20);
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$display("after setting timeformat:");
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$display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
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$display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
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delay_pci(3);
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if($simtime !== 15000) fail = 1;
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if($time !== 150) fail = 1;
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#15;
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if($simtime !== 16500) fail = 1;
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if($time !== 165) fail = 1;
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#(`PCI_CLK_PERIOD);
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if($simtime !== 18000) fail = 1;
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if($time !== 180) fail = 1;
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#(`PCI_CLK_PERIOD *2);
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if($simtime !== 21000) fail = 1;
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if($time !== 210) fail = 1;
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$display("\t\t**********************************************");
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if(fail) $display("\t\t****** time representation test BAD *******");
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else $display("\t\t****** time representation test OK *******");
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$display("\t\t**********************************************\n");
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$finish(0);
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end
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task delay_pci;
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input delta;
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integer delta;
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integer ii;
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begin
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#(`PCI_CLK_PERIOD * delta);
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end
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endtask
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endmodule
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