22 lines
354 B
Coq
22 lines
354 B
Coq
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// Check that an expression is correctly detected to contain an automatic
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// variable if the variable is in a SystemVerilog size cast expression.
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module automatic_error;
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reg g;
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task automatic auto_task;
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reg l;
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begin: block
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assign g = 1'(l);
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end
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endtask
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initial begin
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auto_task;
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$display("FAILED");
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end
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endmodule
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