119 lines
2.9 KiB
ReStructuredText
119 lines
2.9 KiB
ReStructuredText
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Waveforms With GTKWave
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======================
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GTKWave is a VCD waveform viewer based on the GTK library. This viewer support
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VCD and LXT formats for signal dumps. GTKWAVE is available on github
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`here <https://github.com/gtkwave/gtkwave>`_. Most Linux distributions already
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include gtkwave prepackaged.
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.. image:: GTKWave_Example2.png
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Generating VCD/FST files for GTKWAVE ------------------------------------
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Waveform dumps are written by the Icarus Verilog runtime program vvp. The user
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uses $dumpfile and $dumpvars system tasks to enable waveform dumping, then the
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vvp runtime takes care of the rest. The output is written into the file
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specified by the $dumpfile system task. If the $dumpfile call is absent, the
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compiler will choose the file name dump.vcd or dump.lxt or dump.fst, depending
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on runtime flags. The example below dumps everything in and below the test
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module:
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.. code-block:: verilog
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// Do this in your test bench
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0,test);
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end
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By default, the vvp runtime will generate VCD dump output. This is the default
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because it is the most portable. However, when using gtkwave, the FST output
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format is faster and most compact. Use the "-fst" extended argument to
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activate LXT output. For example, if your compiled output is written into the
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file "foo.vvp", the command:
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.. code-block:: console
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% vvp foo.vvp -fst <other-plusargs>
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will cause the dumpfile output to be written in FST format. Absent any
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specific $dumpfile command, this file will be called dump.fst, which can be
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viewed with the command:
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.. code-block:: console
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% gtkwave dump.fst
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A Working Example
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-----------------
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First, the design itself:
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.. code-block:: verilog
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module counter(out, clk, reset);
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parameter WIDTH = 8;
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output [WIDTH-1 : 0] out;
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input clk, reset;
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reg [WIDTH-1 : 0] out;
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wire clk, reset;
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always @(posedge clk)
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out <= out + 1;
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always @reset
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if (reset)
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assign out = 0;
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else
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deassign out;
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endmodule // counter
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Then the simulation file:
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.. code-block:: verilog
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module test;
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/* Make a reset that pulses once. */
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reg reset = 0;
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initial begin
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$dumpfile("test.vcd");
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$dumpvars(0,test);
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# 17 reset = 1;
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# 11 reset = 0;
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# 29 reset = 1;
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# 5 reset =0;
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# 513 $finish;
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end
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/* Make a regular pulsing clock. */
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reg clk = 0;
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always #1 clk = !clk;
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wire [7:0] value;
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counter c1 (value, clk, reset);
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initial
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$monitor("At time %t, value = %h (%0d)",
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$time, value, value);
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endmodule // test
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Compile, run, and view waveforms with these commands:
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.. code-block:: console
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% iverilog -o dsn counter_tb.v counter.v
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% vvp dsn
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% gtkwave test.vcd &
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Click on the 'test', then 'c1' in the top left box on GTKWAVE, then drag the
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signals to the Signals box. You will be able to add signals to display,
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scanning by scope.
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