35 lines
751 B
Systemverilog
35 lines
751 B
Systemverilog
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// Virtual-interface vertical slice (UVM Tier A #3).
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// Note: this slice requires the `interface` keyword in the type
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// (`virtual interface bus_if`) to avoid parser conflicts with `virtual class`.
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interface bus_if;
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logic clk;
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logic [7:0] data;
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endinterface
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class driver;
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virtual interface bus_if vif;
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function new(virtual interface bus_if i);
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vif = i;
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endfunction
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task drive(logic [7:0] d);
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@(posedge vif.clk);
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vif.data = d;
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endtask
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endclass
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module top;
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bus_if bif();
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driver drv;
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initial begin
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bif.clk = 0;
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forever #5 bif.clk = ~bif.clk;
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end
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initial begin
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drv = new(bif);
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#12 drv.drive(8'hA5);
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if (bif.data !== 8'hA5) $fatal(1, "FAILED");
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$display("PASSED");
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$finish;
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end
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endmodule
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