2001-07-26 05:13:51 +02:00
|
|
|
.TH vvp 1 "$Date: 2001/07/26 03:13:51 $" Version "$Date: 2001/07/26 03:13:51 $"
|
2001-07-21 06:34:25 +02:00
|
|
|
.SH NAME
|
|
|
|
|
vvp - Icarus Verilog vvp runtime engine
|
|
|
|
|
|
|
|
|
|
.SH SYNOPSIS
|
|
|
|
|
.B vvp
|
2001-07-21 23:15:51 +02:00
|
|
|
[-dv] [-Mpath] [-mmodule] [-llogfile] inputfile
|
2001-07-21 06:34:25 +02:00
|
|
|
|
|
|
|
|
.SH DESCRIPTION
|
|
|
|
|
.PP
|
|
|
|
|
\fIvvp\fP is the run time engine that executes the default compiled
|
|
|
|
|
form generated by Icarus Verilog. The output from the \fIiverilog\fP
|
|
|
|
|
command is not by itself executable on any platform. Instead, the
|
|
|
|
|
\fIvvp\fP program is invoked to execute the generated output file.
|
|
|
|
|
|
|
|
|
|
.SH OPTIONS
|
|
|
|
|
.l
|
|
|
|
|
\fIvvp\fP accepts the following options:
|
|
|
|
|
.TP 8
|
2001-07-21 23:15:51 +02:00
|
|
|
.B -l\fIlogfile\fP
|
|
|
|
|
This flag specifies a logfile where all MCI <stdlog> output goes.
|
|
|
|
|
Specify logfile as '-' to send log output to <stderr>. $display and
|
|
|
|
|
friends send their output both to <stdout> and <stdlog>.
|
|
|
|
|
.TP 8
|
2001-07-21 06:34:25 +02:00
|
|
|
.B -M\fIpath\fP
|
2001-07-26 05:13:51 +02:00
|
|
|
This flag adds a directory to the path list used to locate VPI
|
|
|
|
|
modules. The default path includes only the install directory for the
|
|
|
|
|
system.vpi module, but this flag can add other directories. Multiple
|
|
|
|
|
paths are allowed, and modules will be searched in order.
|
2001-07-21 06:34:25 +02:00
|
|
|
.TP 8
|
|
|
|
|
.B -m\fImodule\fP
|
|
|
|
|
Tell the vvp run time to load the named module before executing the
|
|
|
|
|
simulation. The \fBsystem.vpi\fP module is loaded by default, but
|
|
|
|
|
additional modules, including modules that you compiled locally, can
|
|
|
|
|
be specified with this flag. Any number of modules can be loaded, and
|
|
|
|
|
they will be linked in the order they are listed on the command line.
|
|
|
|
|
.TP 8
|
|
|
|
|
.B -v
|
|
|
|
|
Turn on verbose messages. This will cause information about run time
|
|
|
|
|
progress to be printed to standard out.
|
|
|
|
|
|
|
|
|
|
.SH "AUTHOR"
|
|
|
|
|
.nf
|
|
|
|
|
Steve Williams (steve@icarus.com)
|
|
|
|
|
|
|
|
|
|
.SH SEE ALSO
|
|
|
|
|
.BR "<http://www.icarus.com/eda/verilog/>"
|
|
|
|
|
|
|
|
|
|
.SH COPYRIGHT
|
|
|
|
|
.nf
|
|
|
|
|
Copyright \(co 2001 Stephen Williams
|
|
|
|
|
|
|
|
|
|
This document can be freely redistributed according to the terms of the
|
|
|
|
|
GNU General Public License version 2.0
|
