iverilog/vvp/examples/sum.vvp

:vpi_module "system";

; Copyright (c) 2001-2008  Stephen Williams (steve@icarus.com)
;
;    This source code is free software; you can redistribute it
;    and/or modify it in source code form under the terms of the GNU
;    General Public License as published by the Free Software
;    Foundation; either version 2 of the License, or (at your option)
;    any later version.
;
;    This program is distributed in the hope that it will be useful,
;    but WITHOUT ANY WARRANTY; without even the implied warranty of
;    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;    GNU General Public License for more details.
;
;    You should have received a copy of the GNU General Public License
;    along with this program; if not, write to the Free Software
;    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA

; This example shows how to wire up a simple adder. The code below is
; like what might be generated from the Verilog:
;
;    module main;
;      reg [3:0] A, B;
;      wire [3:0] Q = A + B;
;
;      initial begin
;        A = 2;
;        B = 3;
;        #1 $display("%b  %b = %b", A, B, Q);
;      end
;    endmodule
;
; Notice the use of the .arith/sum statement, including the specification
; of the width (4 bits) and the order that the bits of the operands are
; passed to the statement.


S_main .scope module, "main";

A    .var	"A", 3 0;
B    .var	"B", 3 0;
Q    .net	"Q", 3 0, add;

add  .arith/sum	4, A, B;


start	%movi 8, 2, 4; Load a 4 bit value (2) into location 8
	%set/v	A, 8, 4;
	%movi 8, 3, 4; Ditto except the value is 3
	%set/v	B, 8, 4;

	%delay	1, 0;

	%vpi_call 0 0 "$display", "%b + %b == %b", A, B, Q;
	%end;
	.thread start;
:file_names 2;
    "N/A";
    "<interactive>";