iverilog/ivtest/fpga_tests/onehot16.v

mirror of https://github.com/steveicarus/iverilog.git
module onehot16(output wire [15:0] out, input wire [3:0] A);

   assign out = 1 << A;

endmodule
Add ivtest to the iverilog source tree By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature. 2022-01-15 19:18:50 +01:00			`module onehot16(output wire [15:0] out, input wire [3:0] A);`

			`assign out = 1 << A;`

			`endmodule`