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9.8 KiB
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226 lines
9.8 KiB
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<!DOCTYPE html>
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<html lang="en" data-content_root="../../../">
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<title>Xilinx Hint — Icarus Verilog documentation</title>
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<div class="document">
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<div class="body" role="main">
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<section id="xilinx-hint">
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<h1>Xilinx Hint<a class="headerlink" href="#xilinx-hint" title="Link to this heading">¶</a></h1>
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<p>For those of you who wish to use Icarus Verilog, in combination with
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the Xilinx back end (Foundation or Alliance), it can be done. I have
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run some admittedly simple (2300 equivalent gates) designs through this
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setup, targeting a Spartan XCS10.</p>
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<section id="verilog">
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<h2>Verilog:<a class="headerlink" href="#verilog" title="Link to this heading">¶</a></h2>
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<p>Older versions of Icarus Verilog (like 19990814) couldn’t synthesize
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logic buried in procedural (flip-flop) assignment. Newer versions
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(like 20000120) don’t have this limitation.</p>
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<p>Procedural assignments have to be given one at a time, to be
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“found” by xnfsyn. Say</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>always @ (posedge Clk) Y = newY;
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always @ (posedge Clk) Z = newZ;
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</pre></div>
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</div>
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<p>rather than</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>always @ (posedge Clk) begin
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Y = newY;
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Z = newZ;
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end
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</pre></div>
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</div>
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<p>Steve’s xnf.txt covers most buffer and pin constructs, but I had reason
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to use a global clock net not connected to an input pin. The standard
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Verilog for a buffer, combined with a declaration to turn that into a
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BUFG, is:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>buf BUFG( your_output_here, your_input_here );
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$attribute(BUFG,"XNF-LCA","BUFG:O,I")
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</pre></div>
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</div>
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<p>I use post-processing on my .xnf files to add “FAST” attributes to
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output pins.</p>
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</section>
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<section id="running-ivl">
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<h2>Running ivl:<a class="headerlink" href="#running-ivl" title="Link to this heading">¶</a></h2>
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<p>The -F switches are important. The following order seems to robustly
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generate valid XNF files, and is used by “verilog -X”:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>-Fsynth -Fnodangle -Fxnfio
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</pre></div>
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</div>
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</section>
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<section id="generating-pcf-files">
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<h2>Generating .pcf files:<a class="headerlink" href="#generating-pcf-files" title="Link to this heading">¶</a></h2>
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<p>The ngdbuild step seems to lose pin placement information that ivl
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puts in the XNF file. Use xnf2pcf to extract this information to
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a .pcf file, which the Xilinx place-and-route software _will_ pay
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attention to. Steve says he now makes that information available
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in an NCF file, with -fncf=<path>, but I haven’t tested that.</p>
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<p>Running the Xilinx back end:</p>
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<p>You can presumably use the GUI, but that doesn’t fit in Makefiles :-).
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Here is the command sequence in pseudo-shell-script:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>ngdbuild -p $part $1.xnf $1.ngd
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map -p $part -o map.ncd $1.ngd
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xnf2pcf <$1.xnf >$1.pcf # see above
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par -w -ol 2 -d 0 map.ncd $1.ncd $1.pcf
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bitgen_flags = -g ConfigRate:SLOW -g TdoPin:PULLNONE -g DonePin:PULLUP \
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-g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no \
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-g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 \
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-g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable
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bitgen $1.ncd -l -w $bitgen_flags
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</pre></div>
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</div>
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<p>The Xilinx software has diarrhea of the temp files (14, not including
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.xnf, .pcf, .ngd, .ncd, and .bit), so this sequence is best done in a
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dedicated directory. Note in particular that map.ncd is a generic name.</p>
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<p>I had reason to run this remotely (and transparently within a Makefile)
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via ssh. I use the gmake rule:</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>%.bit : %.xnf
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ssh -x -a -o 'BatchMode yes' ${ALLIANCE_HOST} \
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remote_alliance ${REMOTE_DIR} $(basename $@) 2>&1 < $<
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scp ${ALLIANCE_HOST}:${REMOTE_DIR}/$@ .
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</pre></div>
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</div>
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<p>and the remote_alliance script (on ${ALLIANCE_HOST}):</p>
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<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>/bin/csh
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cd $1
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cat >! $2.xnf
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xnf2pcf <$2.xnf >! $2.pcf
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./backend $2
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</pre></div>
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</div>
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<p>There is now a “Xilinx on Linux HOWTO” at <a class="reference external" href="http://www.polybus.com/xilinx_on_linux.html">http://www.polybus.com/xilinx_on_linux.html</a>
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I haven’t tried this yet, it looks interesting.</p>
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</section>
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<section id="downloading">
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<h2>Downloading:<a class="headerlink" href="#downloading" title="Link to this heading">¶</a></h2>
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<p>I use the XESS (<a class="reference external" href="http://www.xess.com/">http://www.xess.com/</a>) XSP-10 development board, which
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uses the PC parallel (printer) port for downloading and interaction
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with the host. They made an old version of their download program
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public domain, posted it at <a class="reference external" href="http://www.xess.com/FPGA/xstools.zip">http://www.xess.com/FPGA/xstools.zip</a> ,
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and now there is a Linux port at <a class="reference external" href="ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz">ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz</a> .</p>
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<p>The above hints are based on my experience with Foundation 1.5 on NT
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(gack) and Alliance 2.1i on Solaris. Your mileage may vary. Good luck!</p>
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<blockquote>
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<div><ul class="simple">
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<li><dl class="simple">
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<dt>Larry Doolittle <<a class="reference external" href="mailto:LRDoolittle%40lbl.gov">LRDoolittle<span>@</span>lbl<span>.</span>gov</a>> August 19, 1999</dt><dd><p>updated February 1, 2000</p>
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</dd>
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</dl>
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</li>
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</ul>
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</div></blockquote>
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</section>
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</section>
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</div>
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</div>
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</div>
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<div class="sphinxsidebar" role="navigation" aria-label="main navigation">
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<div class="sphinxsidebarwrapper">
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<h1 class="logo"><a href="../../../index.html">Icarus Verilog</a></h1>
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<h3>Navigation</h3>
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<p class="caption" role="heading"><span class="caption-text">Contents:</span></p>
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<ul class="current">
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<li class="toctree-l1"><a class="reference internal" href="../../../usage/index.html">Icarus Verilog Usage</a></li>
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<li class="toctree-l1"><a class="reference internal" href="../../../targets/index.html">The Icarus Verilog Targets</a></li>
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<li class="toctree-l1 current"><a class="reference internal" href="../../index.html">Icarus Verilog Developer Support</a><ul class="current">
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<li class="toctree-l2"><a class="reference internal" href="../../getting_started.html">Getting Started as a Contributor</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../regression_tests.html">The Regression Test Suite</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../version_stamps.html">Files With Version Information</a></li>
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<li class="toctree-l2 current"><a class="reference internal" href="../index.html">Developer Guide</a></li>
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<li class="toctree-l2"><a class="reference internal" href="../../glossary.html">Glossary</a></li>
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<li><a href="../../../index.html">Documentation overview</a><ul>
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<li><a href="index.html">Miscellaneous</a><ul>
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<li>Previous: <a href="swift.html" title="previous chapter">Swift Model Support (Preliminary)</a></li>
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©2024-2025, Stephen Williams.
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