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Updated Adding support for new devices. (markdown)
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@ -74,3 +74,7 @@ As soon as iceunpack is able to at least load the binary bit-stream it can come
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Above I briefly discussed the `.glb files` created by `icecube.sh`. The script `icefuzz/glbcheck.py` can be used to compare a `.glb` dump file with an ASCII file generated by `iceunpack`. This should help a lot with debugging problems with `icepack.cc`.
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Verification is key! Make sure to set up a small set of examples and write tiny scripts that help you track the mismatches between the generated `.asc` and `.glb` using `glbcheck.py`. Usually when I get stuck in a reverse engineering project, as soon as I have implemented a way to measure my progress, I quickly start making progress again.
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Luckily, the `icefuzz` directory contains a number of python scripts which can generate sample Verilog. You can run these auto-generated files through iCEcube by running `make`. This defaults to the 1k device but you can add additional devices to the `Makefile` and `fuzzconfig.py` file. (Note, @tannewt is changing the way to select the device to `make ICEDEVICE=5k` for example.)
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In `fuzzconfig.py` you'll need to provide a list of pins in `pins`, the number of ram blocks in `num_ramb40` and the list of global buffer pins in `gpins`. Global buffer pins are those that can be used to provide high drive signals through the whole array for signals such as clock and reset. The list of pins is most easily found in the Package view within iCEcube2. This view also marks pisn as GBIN which go into `gpins`. The number of ram blocks can be counted off of the Floor Planner view in iCEcube2.
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