mirror of https://github.com/YosysHQ/icestorm.git
35 lines
580 B
Verilog
35 lines
580 B
Verilog
module top #(
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parameter NUM_BITS = 8
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) (
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input [NUM_BITS-1:0] clk,
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output reg [NUM_BITS-1:0] y
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);
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wire [NUM_BITS-1:0] t1;
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reg [NUM_BITS-1:0] t2;
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genvar i;
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generate for (i = 0; i < NUM_BITS; i = i+1) begin:bitslice
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SB_RAM40_4K #(
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.READ_MODE(0),
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.WRITE_MODE(0)
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) ram40 (
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.WADDR(8'b0),
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.RADDR(8'b0),
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.MASK(~16'b0),
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.WDATA(8'b0),
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.RDATA(t1[i]),
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.WE(1'b1),
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.WCLKE(1'b1),
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.WCLK(clk[i]),
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.RE(1'b1),
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.RCLKE(1'b1),
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.RCLK(clk[i])
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);
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always @(posedge clk[i]) begin
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t2[i] <= t1[i];
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y[i] <= t2[i];
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end
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end endgenerate
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endmodule
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