mirror of https://github.com/YosysHQ/icestorm.git
65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
module top(
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input clk,
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input rst,
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input [7:0] a,
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input [7:0] b,
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output [15:0] y);
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wire co;
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wire [31:0] out;
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SB_MAC16 i_sbmac16
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(
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.A(a),
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.B(b),
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.C(8'd0),
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.D(8'd0),
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.O(out),
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.CLK(clk),
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.IRSTTOP(rst),
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.IRSTBOT(rst),
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.ORSTTOP(rst),
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.ORSTBOT(rst),
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.AHOLD(1'b0),
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.BHOLD(1'b0),
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.CHOLD(1'b0),
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.DHOLD(1'b0),
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.OHOLDTOP(1'b0),
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.OHOLDBOT(1'b0),
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.OLOADTOP(1'b0),
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.OLOADBOT(1'b0),
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.ADDSUBTOP(1'b0),
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.ADDSUBBOT(1'b0),
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.CO(co),
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.CI(1'b0),
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.ACCUMCI(),
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.ACCUMCO(),
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.SIGNEXTIN(),
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.SIGNEXTOUT()
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);
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//Config: mult_8x8_pipeline_unsigned
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defparam i_sbmac16. B_SIGNED = 1'b0;
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defparam i_sbmac16. A_SIGNED = 1'b0;
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defparam i_sbmac16. MODE_8x8 = 1'b1;
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defparam i_sbmac16. BOTADDSUB_CARRYSELECT = 2'b00;
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defparam i_sbmac16. BOTADDSUB_UPPERINPUT = 1'b0;
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defparam i_sbmac16. BOTADDSUB_LOWERINPUT = 2'b00;
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defparam i_sbmac16. BOTOUTPUT_SELECT = 2'b10;
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defparam i_sbmac16. TOPADDSUB_CARRYSELECT = 2'b00;
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defparam i_sbmac16. TOPADDSUB_UPPERINPUT = 1'b0;
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defparam i_sbmac16. TOPADDSUB_LOWERINPUT = 2'b00;
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defparam i_sbmac16. TOPOUTPUT_SELECT = 2'b10;
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defparam i_sbmac16. PIPELINE_16x16_MULT_REG2 = 1'b0;
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defparam i_sbmac16. PIPELINE_16x16_MULT_REG1 = 1'b1;
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defparam i_sbmac16. BOT_8x8_MULT_REG = 1'b1;
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defparam i_sbmac16. TOP_8x8_MULT_REG = 1'b1;
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defparam i_sbmac16. D_REG = 1'b0;
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defparam i_sbmac16. B_REG = 1'b1;
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defparam i_sbmac16. A_REG = 1'b1;
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defparam i_sbmac16. C_REG = 1'b0;
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assign y = out[15:0];
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endmodule |