mirror of https://github.com/YosysHQ/icestorm.git
19 lines
386 B
Verilog
19 lines
386 B
Verilog
module top (
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inout pin,
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input latch_in,
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output din_0,
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output global
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);
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SB_GB_IO #(
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.PIN_TYPE(6'b 0000_11),
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.PULLUP(1'b 0),
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.NEG_TRIGGER(1'b 0),
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.IO_STANDARD("SB_LVCMOS")
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) \pin_gb_io (
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.PACKAGE_PIN(pin),
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.LATCH_INPUT_VALUE(latch_in),
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.D_IN_0(din_0),
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.GLOBAL_BUFFER_OUTPUT(globals)
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);
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endmodule
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