mirror of https://github.com/YosysHQ/icestorm.git
58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
module top (
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input clk,
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input RX,
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output TX,
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output reg LED1,
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output reg LED2,
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output reg LED3,
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output reg LED4,
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output reg LED5
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);
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parameter integer BAUD_RATE = 9600;
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parameter integer CLOCK_FREQ_HZ = 12000000;
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localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);
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reg [7:0] buffer;
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reg buffer_valid;
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reg [$clog2(3*HALF_PERIOD):0] cycle_cnt;
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reg [3:0] bit_cnt = 0;
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reg recv = 0;
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always @(posedge clk) begin
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buffer_valid <= 0;
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if (!recv) begin
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if (!RX) begin
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cycle_cnt <= HALF_PERIOD;
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bit_cnt <= 0;
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recv <= 1;
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end
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end else begin
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if (cycle_cnt == 2*HALF_PERIOD) begin
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cycle_cnt <= 0;
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bit_cnt <= bit_cnt + 1;
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if (bit_cnt == 9) begin
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buffer_valid <= 1;
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recv <= 0;
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end else begin
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buffer <= {RX, buffer[7:1]};
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end
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end else begin
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cycle_cnt <= cycle_cnt + 1;
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end
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end
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end
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always @(posedge clk) begin
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if (buffer_valid) begin
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if (buffer == "1") LED1 <= !LED1;
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if (buffer == "2") LED2 <= !LED2;
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if (buffer == "3") LED3 <= !LED3;
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if (buffer == "4") LED4 <= !LED4;
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if (buffer == "5") LED5 <= !LED5;
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end
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end
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assign TX = RX;
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endmodule
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