mirror of https://github.com/YosysHQ/icestorm.git
29 lines
470 B
Verilog
29 lines
470 B
Verilog
module top (
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input clk,
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output LED1, LED2, LED3, LED4, LED5
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);
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localparam LOG2DELAY = 22;
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reg [LOG2DELAY-1:0] counter = 0;
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reg [3:0] counter2 = 0;
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reg state = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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counter2 <= counter2 + !counter;
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state <= state ^ !counter;
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end
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assign LED1 = state;
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assign LED2 = 0;
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assign LED3 = 0;
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assign LED4 = 0;
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assign LED5 = 1;
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SB_WARMBOOT WB (
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.BOOT(&counter2),
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.S1(1'b 0),
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.S0(1'b 1)
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);
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endmodule
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