mirror of https://github.com/YosysHQ/icestorm.git
34 lines
740 B
Verilog
34 lines
740 B
Verilog
module top(input clk,
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output [4:0] led,
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input [7:0] pmod,
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//spi interface
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output spi_miso,
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input spi_mosi,
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input spi_clk,
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input spi_cs_n);
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//parameter SPI_MODE = 1; // CPOL = 0, CPHA = 1
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reg [8:0] fifo = 8'd0;
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reg [2:0] counter = 0;
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always @ (negedge spi_clk)
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begin
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fifo <= {fifo[7:0],spi_mosi}; // loopback fifo
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if(counter < 4'd7) begin
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counter <= counter + 1;
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end
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else begin
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counter <= 0;
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led <={fifo[3:0],spi_mosi};
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end
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end
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always @ (posedge spi_clk)
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begin
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spi_miso<=fifo[7]; // loopback
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//spi_miso<=pmod[counter]; //logic analyzer
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end
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endmodule // top
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