mirror of https://github.com/YosysHQ/icestorm.git
72 lines
1.8 KiB
Verilog
72 lines
1.8 KiB
Verilog
module top(
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input clk,
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input rstn,
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output LED1,
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output LED2);
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wire reset = !rstn;
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wire [15:0] A = 16'd999;
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wire [15:0] B = 16'd12345;
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wire [31:0] RES = 32'd12332655;
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wire [31:0] dsp_out;
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SB_MAC16 i_sbmac16
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(
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.A(A),
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.B(B),
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.C(16'b0),
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.D(16'b0),
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.CLK(clk),
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.CE(1'b1),
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.IRSTTOP(reset),
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.IRSTBOT(reset),
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.ORSTTOP(reset),
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.ORSTBOT(reset),
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.AHOLD(1'b0),
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.BHOLD(1'b0),
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.CHOLD(1'b0),
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.DHOLD(1'b0),
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.OHOLDTOP(1'b0),
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.OHOLDBOT(1'b0),
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.OLOADTOP(1'b0),
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.OLOADBOT(1'b0),
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.ADDSUBTOP(1'b0),
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.ADDSUBBOT(1'b0),
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.CO(),
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.CI(1'b0),
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.O(dsp_out)
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);
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//16x16 => 32 unsigned pipelined multiply
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defparam i_sbmac16. B_SIGNED = 1'b0;
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defparam i_sbmac16. A_SIGNED = 1'b0;
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defparam i_sbmac16. MODE_8x8 = 1'b0;
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defparam i_sbmac16. BOTADDSUB_CARRYSELECT = 2'b00;
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defparam i_sbmac16. BOTADDSUB_UPPERINPUT = 1'b0;
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defparam i_sbmac16. BOTADDSUB_LOWERINPUT = 2'b00;
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defparam i_sbmac16. BOTOUTPUT_SELECT = 2'b11;
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defparam i_sbmac16. TOPADDSUB_CARRYSELECT = 2'b00;
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defparam i_sbmac16. TOPADDSUB_UPPERINPUT = 1'b0;
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defparam i_sbmac16. TOPADDSUB_LOWERINPUT = 2'b00;
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defparam i_sbmac16. TOPOUTPUT_SELECT = 2'b11;
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defparam i_sbmac16. PIPELINE_16x16_MULT_REG2 = 1'b1;
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defparam i_sbmac16. PIPELINE_16x16_MULT_REG1 = 1'b1;
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defparam i_sbmac16. BOT_8x8_MULT_REG = 1'b1;
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defparam i_sbmac16. TOP_8x8_MULT_REG = 1'b1;
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defparam i_sbmac16. D_REG = 1'b0;
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defparam i_sbmac16. B_REG = 1'b1;
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defparam i_sbmac16. A_REG = 1'b1;
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defparam i_sbmac16. C_REG = 1'b0;
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assign LED1 = (dsp_out == RES) ? 1'b1 : 1'b0;
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assign LED2 = 1'b0;
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endmodule
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