mirror of https://github.com/YosysHQ/icestorm.git
127 lines
3.4 KiB
Verilog
127 lines
3.4 KiB
Verilog
module testbench;
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reg pin_reg;
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reg latch_in;
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reg clk_en;
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reg clk_in;
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reg clk_out;
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reg oen;
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reg dout_0;
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reg dout_1;
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wire gold_pin;
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wire gold_global;
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wire gold_din_0;
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wire gold_din_1;
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wire gate_pin;
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wire gate_global;
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wire gate_din_0;
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wire gate_din_1;
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top gold (
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.pin (gold_pin ),
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.global (gold_global),
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.latch_in(latch_in ),
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.clk_en (clk_en ),
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.clk_in (clk_in ),
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.clk_out (clk_out ),
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.oen (oen ),
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.dout_0 (dout_0 ),
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.dout_1 (dout_1 ),
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.din_0 (gold_din_0 ),
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.din_1 (gold_din_1 )
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);
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chip gate (
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.pin (gate_pin ),
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.global (gate_global),
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.latch_in(latch_in ),
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.clk_en (clk_en ),
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.clk_in (clk_in ),
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.clk_out (clk_out ),
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.oen (oen ),
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.dout_0 (dout_0 ),
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.dout_1 (dout_1 ),
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.din_0 (gate_din_0 ),
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.din_1 (gate_din_1 )
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);
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assign gold_pin = pin_reg;
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assign gate_pin = pin_reg;
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reg [63:0] xorshift64_state = 64'd88172645463325252;
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg error = 0;
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integer rndval;
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initial begin
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`ifdef VCDFILE
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$dumpfile(`VCDFILE);
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$dumpvars(0, testbench);
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`endif
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pin_reg <= 0;
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latch_in <= 0;
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clk_en <= 1;
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clk_in <= 0;
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clk_out <= 0;
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oen <= 0;
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dout_0 <= 0;
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dout_1 <= 0;
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pin_reg <= 0;
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repeat (5) #10 clk_in <= ~clk_in;
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repeat (5) #10 clk_out <= ~clk_out;
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pin_reg <= 1;
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repeat (5) #10 clk_in <= ~clk_in;
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repeat (5) #10 clk_out <= ~clk_out;
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pin_reg <= 'bz;
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repeat (5) #10 clk_in <= ~clk_in;
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repeat (5) #10 clk_out <= ~clk_out;
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repeat (1000) begin
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if ('b `INTYPE == 0) begin
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error = {gold_pin, gold_global, gold_din_0, gate_din_1} !== {gate_pin, gate_global, gate_din_0, gate_din_1};
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$display({"pin=%b%b, global=%b%b, latch_in=%b, clk_en=%b, clk_in=%b, clk_out=%b, ",
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"oen=%b, dout_0=%b, dout_1=%b, din_0=%b%b, din_1=%b%b %s"},
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gold_pin, gate_pin, gold_global, gate_global, latch_in, clk_en, clk_in, clk_out,
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oen, dout_0, dout_1, gold_din_0, gate_din_0, gold_din_1, gate_din_1, error ? "ERROR" : "OK");
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end else begin
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error = {gold_pin, gold_global, gold_din_0} !== {gate_pin, gate_global, gate_din_0};
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$display({"pin=%b%b, global=%b%b, latch_in=%b, clk_en=%b, clk_in=%b, clk_out=%b, ",
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"oen=%b, dout_0=%b, dout_1=%b, din_0=%b%b %s"},
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gold_pin, gate_pin, gold_global, gate_global, latch_in, clk_en, clk_in, clk_out,
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oen, dout_0, dout_1, gold_din_0, gate_din_0, error ? "ERROR" : "OK");
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end
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xorshift64_next;
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rndval = (xorshift64_state >> 16) & 'hffff;
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case (xorshift64_state % 5)
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0: pin_reg <= 1'bz;
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1: pin_reg <= 1'b0;
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2: pin_reg <= 1'b1;
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`ifdef DISABLED
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// Lattice SB_IO clk_en model is b0rken
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// IceBox latch_in routing is non-existing
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default: {latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1} <=
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{latch_in, clk_en, clk_in, clk_out, oen, dout_0, dout_1} ^ (1 << (rndval % 7));
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`else
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default: {latch_in, clk_in, clk_out, oen, dout_0, dout_1} <=
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{latch_in, clk_in, clk_out, oen, dout_0, dout_1} ^ (1 << (rndval % 6));
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`endif
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endcase
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#10;
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end
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end
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endmodule
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