mirror of https://github.com/YosysHQ/icestorm.git
25 lines
354 B
Verilog
25 lines
354 B
Verilog
module top(
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input clk,
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input [13:0] addr,
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input [7:0] din,
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input wren,
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input cs,
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output [7:0] dout
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);
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SB_SPRAM256KA spram_i
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(
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.ADDRESS(addr),
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.DATAIN(din),
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.MASKWREN(4'b1111),
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.WREN(wren),
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.CHIPSELECT(cs),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b0),
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.DATAOUT(dout)
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);
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endmodule |