mirror of https://github.com/YosysHQ/icestorm.git
81 lines
1.5 KiB
Verilog
81 lines
1.5 KiB
Verilog
// ICEDEV=hx8k-ct256 bash ../icecube.sh sb_ram40.v
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// ../../icebox/icebox_vlog.py -P sb_ram40.psb sb_ram40.txt
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// ../../icebox/icebox_explain.py -t '7 21' sb_ram40.txt
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module top (
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input [10:0] WADDR,
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input [10:0] RADDR,
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input [15:0] MASK,
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input [15:0] WDATA,
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output [15:0] RDATA_0,
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output [ 7:0] RDATA_1,
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output [ 1:0] RDATA_3,
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input WE, WCLKE, WCLK,
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input RE, RCLKE, RCLK,
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output X
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);
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// Write Mode 0: 8 Bit ADDR, 16 Bit DATA, MASK
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// Write Mode 1: 9 Bit ADDR, 8 Bit DATA, NO MASK
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// Write Mode 2: 10 Bit ADDR, 4 Bit DATA, NO MASK
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// Write Mode 3: 11 Bit ADDR, 2 Bit DATA, NO MASK
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SB_RAM40_4K #(
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.READ_MODE(0),
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.WRITE_MODE(0)
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) ram40_00 (
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.WADDR(WADDR[7:0]),
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.RADDR(RADDR[7:0]),
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.MASK(MASK),
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.WDATA(WDATA),
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.RDATA(RDATA_0),
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.WE(WE),
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.WCLKE(WCLKE),
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.WCLK(WCLK),
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.RE(RE),
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.RCLKE(RCLKE),
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.RCLK(RCLK)
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);
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SB_RAM40_4K #(
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.READ_MODE(1),
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.WRITE_MODE(2)
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) ram40_12 (
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.WADDR(WADDR[9:0]),
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.RADDR(RADDR[8:0]),
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.WDATA(WDATA[3:0]),
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.RDATA(RDATA_1),
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.WE(WE),
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.WCLKE(WCLKE),
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.WCLK(WCLK),
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.RE(RE),
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.RCLKE(RCLKE),
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.RCLK(RCLK)
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);
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SB_RAM40_4K #(
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.READ_MODE(3),
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.WRITE_MODE(3)
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) ram40_33 (
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.WADDR(WADDR),
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.RADDR(RADDR),
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.WDATA(WDATA[1:0]),
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.RDATA(RDATA_3),
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.WE(WE),
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.WCLKE(WCLKE),
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.WCLK(WCLK),
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.RE(RE),
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.RCLKE(RCLKE),
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.RCLK(RCLK)
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);
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SB_LUT4 #(
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.LUT_INIT(16'b 1000_0000_0000_0000)
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) lut (
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.O(X),
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.I0(RDATA_0[0]),
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.I1(RDATA_0[6]),
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.I2(RDATA_0[8]),
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.I3(RDATA_0[14])
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);
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endmodule
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