mirror of https://github.com/YosysHQ/icestorm.git
58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
module top(
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input REFERENCECLK,
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output PLLOUTCORE,
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output PLLOUTGLOBAL,
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input EXTFEEDBACK,
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input [7:0] DYNAMICDELAY,
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output LOCK,
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input BYPASS,
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input RESETB,
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input LATCHINPUTVALUE,
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//Test Pins
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output SDO,
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input SDI,
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input SCLK
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);
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("DELAY"),
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// .FEEDBACK_PATH("SIMPLE"),
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// .FEEDBACK_PATH("PHASE_AND_DELAY"),
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// .FEEDBACK_PATH("EXTERNAL"),
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.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
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// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
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.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
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// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
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.PLLOUT_SELECT("GENCLK"),
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// .PLLOUT_SELECT("GENCLK_HALF"),
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// .PLLOUT_SELECT("SHIFTREG_90deg"),
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// .PLLOUT_SELECT("SHIFTREG_0deg"),
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.SHIFTREG_DIV_MODE(1'b0),
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.FDA_FEEDBACK(4'b1111),
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.FDA_RELATIVE(4'b1111),
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.DIVR(4'b0000),
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.DIVF(7'b0000000),
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.DIVQ(3'b001),
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.FILTER_RANGE(3'b000),
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.ENABLE_ICEGATE(1'b0),
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.TEST_MODE(1'b0)
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) uut (
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.REFERENCECLK (REFERENCECLK ),
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.PLLOUTCORE (PLLOUTCORE ),
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.PLLOUTGLOBAL (PLLOUTGLOBAL ),
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.EXTFEEDBACK (EXTFEEDBACK ),
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.DYNAMICDELAY (DYNAMICDELAY ),
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.LOCK (LOCK ),
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.BYPASS (BYPASS ),
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.RESETB (RESETB ),
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.LATCHINPUTVALUE(LATCHINPUTVALUE),
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.SDO (SDO ),
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.SDI (SDI ),
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.SCLK (SCLK )
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);
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endmodule
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