mirror of https://github.com/YosysHQ/icestorm.git
40 lines
678 B
Verilog
40 lines
678 B
Verilog
module top(input clk, inout pin1, inout pin2);
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wire w;
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SB_IO #(
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.PIN_TYPE(6'b 0101_00),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b1),
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.IO_STANDARD("SB_LVCMOS")
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) IO_PIN_1 (
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.PACKAGE_PIN(pin1),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(clk),
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.OUTPUT_CLK(clk),
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.OUTPUT_ENABLE(),
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.D_OUT_0(1'b0),
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.D_OUT_1(1'b0),
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.D_IN_0(w),
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.D_IN_1()
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);
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SB_IO #(
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.PIN_TYPE(6'b 0101_00),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b1),
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.IO_STANDARD("SB_LVCMOS")
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) IO_PIN_2 (
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.PACKAGE_PIN(pin2),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(clk),
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.OUTPUT_CLK(clk),
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.OUTPUT_ENABLE(),
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.D_OUT_0(w),
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.D_OUT_1(1'b0),
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.D_IN_0(),
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.D_IN_1()
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);
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endmodule
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