mirror of https://github.com/YosysHQ/icestorm.git
67 lines
1.1 KiB
Verilog
67 lines
1.1 KiB
Verilog
module top (
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input sbclki, sbrwi, sbstbi,
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input sbadri0, sbadri1, sbadri7,
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input sbdati0, sbdati1, sbdati7,
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output sbdato0, sbdato1, sbdato7,
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output sbacko, i2cirq, i2cwkup,
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inout scl, sda
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);
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wire scli, sclo, scloe, sdai, sdao, sdaoe;
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SB_I2C #(
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.I2C_SLAVE_INIT_ADDR("0b1111100010"),
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.BUS_ADDR74("0b0011")
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) i2c_ip (
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.SBCLKI(sbclki),
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.SBRWI(sbrwi),
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.SBSTBI(sbstbi),
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.SBADRI0(sbadri0),
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.SBADRI1(sbadri1),
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.SBADRI7(sbadri7),
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.SBDATI0(sbdati0),
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.SBDATI1(sbdati1),
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.SBDATI7(sbdati7),
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.SBDATO0(sbdato0),
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.SBDATO1(sbdato1),
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.SBDATO7(sbdato7),
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.SBACKO(sbacko),
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.I2CIRQ(i2cirq),
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.I2CWKUP(i2cwkup),
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.SCLI(scli),
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.SCLO(sclo),
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.SCLOE(scloe),
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.SDAI(sdai),
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.SDAO(sdao),
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.SDAOE(sdaoe)
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) /* synthesis SCL_INPUT_FILTERED=1 */;
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) scl_io (
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.PACKAGE_PIN(scl),
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.OUTPUT_ENABLE(scloe),
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.D_OUT_0(sclo),
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.D_IN_0(scli)
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);
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) sda_io (
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.PACKAGE_PIN(sda),
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.OUTPUT_ENABLE(sdaoe),
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.D_OUT_0(sdao),
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.D_IN_0(sdai)
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);
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endmodule
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