mirror of https://github.com/YosysHQ/icestorm.git
24 lines
319 B
Verilog
24 lines
319 B
Verilog
module top (input a, b, c, d, e, f, g, output y);
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wire cascade;
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SB_LUT4 #(
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.LUT_INIT(16'b 1100_1100_1100_1010)
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) src_lut (
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.O(cascade),
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.I0(a),
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.I1(b),
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.I2(c),
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.I3(d)
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);
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SB_LUT4 #(
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.LUT_INIT(16'b 1000_0100_0010_0001)
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) dst_lut (
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.O(y),
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.I0(e),
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.I1(f),
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.I2(cascade),
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.I3(g)
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);
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endmodule
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