mirror of https://github.com/YosysHQ/icestorm.git
24 lines
378 B
Verilog
24 lines
378 B
Verilog
module top (
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inout pin,
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input latch_in,
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output data_out
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);
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SB_IO #(
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.PIN_TYPE(6'b0000_11),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0),
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.IO_STANDARD("SB_LVCMOS")
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) pin_ibuf (
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.PACKAGE_PIN(pin),
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.LATCH_INPUT_VALUE(latch_in),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(data_out),
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.D_IN_1()
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);
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endmodule
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